1. Field of the Invention
The present invention relates to the field of computer memory, and more particularly, to ultra-dense and ultra-fast random access memory with reasonable power consumption.
2. Background of the Invention
Every computer system requires memory for storing data and programs. There are many different types of memory incorporating a variety of technologies and access times. One important type of memory is a read-only memory in which fixed programs and/or data is stored in the memory and only the read operation is allowed. Thus, a read-only memory is usually written only once at the time of manufacturing. A typical function of a read-only memory is to store programs for algorithms used to calculate various arithmetic functions in small calculators. Another more powerful type of memory is a random-access memory (RAM) in which an operator can both read and write to memory cells and be able to access any cell or a group of cells in the memory. A RAM can be either static or dynamic. A static RAM typically utilizes flip-flops, and retains information written thereto as long as power is applied. In a static RAM, each memory cell may require six or more transistors, as shown in the prior art circuit of FIG. 2. Because a static RAM requires multiple transistors in each cell, its chip packaging density is limited. In addition, the power dissipation of a static RAM may be relatively high. However, the big advantage of a static RAM is its high operating speed. A dynamic RAM, on the other hand, can achieve higher chip packaging density and lower cost per memory cell because of its simple memory cell structure, consisting of one transistor and a small capacitor. Although a dynamic RAM is popular because of its high packaging density, the capacitor will lose its charge over a period of time unless subjected to a periodic refresh cycle. Thus, a dynamic memory may execute both read and write operations, but also requires periodic refresh cycles, unlike a static RAM which can retain its information as long as power is applied.
Traditionally, semiconductor RAMs have used transistors including bipolar transistors and metal-oxide-semiconductor (MOS) devices. Bipolar RAMs incorporate bipolar junction transistors and are manufactured using TTL, SCL or I.sup.2 L technology. Each memory cell utilizes a flip-flop, and the access time is usually in the 20-100 nsec range. Bipolar transistor RAMs have been used in applications where high operating speeds are required at the expense of the relatively large power dissipation. In order to achieve high density packaging, low power dissipation and low manufacturing cost while maintaining reasonable operating speed, MOS devices have been used in computer memories instead of bipolar transistors. Furthermore, transistor sizes have been decreased in order to achieve higher density integration.
The present invention describes a memory cell which comprises a device exhibiting an exponential or linear current-voltage characteristic in series with a device exhibiting N-type negative differential resistance. Although negative differential resistance devices have been used in RAMs (FIGS. 5 and 6), the present invention departs significantly from the past implementation practices, as will be described in detail below. The present invention achieves high speed operations by incorporating (i) transistorless memory cells based on negative differential resistance devices and (ii) the current-mode nature of information storage which provides the additional advantage of higher tolerance to radiation induced charge fluctuations. In addition, in order to achieve high density packaging and a simpler and more tolerant manufacturing process, the present invention's memory cells are fabricated perpendicular to the lithography plane using a self-aligned fabrication process.